//-----------------------------------------------------------------------------
//  Copyright (c) 2013 by HangZhou HenqgQiao Design Corporation. All rights reserved.
//
//  Project  : 
//  Module   : over sample the input data with 8-phases 311M clock
//  Parent   : 
//  Children : 
//
//  Description: 
//
//  Parameters:
//  Local Parameters:
//
//  Notes       : 
//
//  Multicycle and False Paths

module	FRM_RJ0(
   input                         FRM_RESET,
   input                         FRM_RXCLK,

   input[7:0]                    RJ0_IN_RDATA,
   input                         RJ0_IN_RDEN,
   input[1:0]                    RJ0_IN_RFMCNT4,
   input[8:0]                    RJ0_IN_RFMCNT270,
   input[3:0]                    RJ0_IN_RFMCNT9,

   input                         MPI_CLK,
   input                         MPI_J0_MODE,
   input[3:0]                    MPI_RJ0_ADDR,
   output[7:0]                   MPI_RJ0_RD

   );

wire[7:0]               RJ0_RDATA;
wire                    RJ0_RDEN;
wire[1:0]               RJ0_RFMCNT4;
wire[8:0]               RJ0_RFMCNT270;
wire[3:0]               RJ0_RFMCNT9;
reg                     RJ0_MODE;
reg[3:0]                RJ0_CNT;
reg[127:0]              RJ0_REGS;

wire                    RJ0_RAM_CLKA, RJ0_RAM_CLKB;
wire                    RJ0_RAM_WEA;
wire[3:0]               RJ0_RAM_ADDRA, RJ0_RAM_ADDRB;
wire[7:0]               RJ0_RAM_DINA;
wire[7:0]               RJ0_RAM_DOUTB;

  assign RJ0_RDATA[7:0]       = RJ0_IN_RDATA[7:0];
  assign RJ0_RDEN             = RJ0_IN_RDEN;
  assign RJ0_RFMCNT4[1:0]     = RJ0_IN_RFMCNT4[1:0];
  assign RJ0_RFMCNT270[8:0]   = RJ0_IN_RFMCNT270[8:0];
  assign RJ0_RFMCNT9[3:0]     = RJ0_IN_RFMCNT9[3:0];

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      RJ0_MODE                                  <= 1'b0;
   else
      RJ0_MODE                                  <= MPI_J0_MODE;
end

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      RJ0_CNT[3:0]                              <= 4'd0;
   else begin
      if ( RJ0_MODE==1'b0 )
         RJ0_CNT[3:0]                           <= 4'd0;
      else begin
         if ( RJ0_RFMCNT9[3:0]==4'd0 && RJ0_RFMCNT270[8:0]==9'd6 && RJ0_RFMCNT4[1:0]==2'd0 && RJ0_RDEN==1'b1 && RJ0_RDATA[7]==1'b1 )
            RJ0_CNT[3:0]                        <= 4'd0;
         else if ( RJ0_RFMCNT9[3:0]==4'd8 && RJ0_RFMCNT270[8:0]==9'd269 && RJ0_RFMCNT4[1:0]==2'd3 && RJ0_RDEN==1'b1 )
            RJ0_CNT[3:0]                        <= RJ0_CNT[3:0] +4'd1;
      end
   end
end



  assign  RJ0_RAM_CLKA      = FRM_RXCLK;
  assign  RJ0_RAM_WEA       = RJ0_RFMCNT9[3:0]==4'd0 && RJ0_RFMCNT270[8:0]==9'd6 && RJ0_RFMCNT4[1:0]==2'd0 && RJ0_RDEN==1'b1;
  assign  RJ0_RAM_ADDRA[3:0]= RJ0_CNT[3:0];
  assign  RJ0_RAM_DINA[7:0] = RJ0_RDATA[7:0];

  assign  RJ0_RAM_CLKB      = MPI_CLK;
  assign  RJ0_RAM_ADDRB[3:0]= MPI_RJ0_ADDR[3:0];
  assign  MPI_RJ0_RD[7:0]   = RJ0_RAM_DOUTB[7:0];
FRM_RJ0_SDP128_8_8                     INST_RJ0_RAM(
   .CLKA                               ( RJ0_RAM_CLKA ),
   .WEA                                ( RJ0_RAM_WEA ),
   .ADDRA                              ( RJ0_RAM_ADDRA[3:0] ),
   .DINA                               ( RJ0_RAM_DINA[7:0] ),

   .CLKB                               ( RJ0_RAM_CLKB ),
   .ADDRB                              ( RJ0_RAM_ADDRB[3:0] ),
   .DOUTB                              ( RJ0_RAM_DOUTB[7:0] )
   );




endmodule
